Thin film transistor array panel for liquid crystal display and method for manufacturing the same

ABSTRACT

In a method of fabricating a liquid crystal display, an insulating layer for storage capacitors is reduced in thickness to increase the storage capacity while maintaining the aperture ratio in a stable manner. A thin film transistor array panel for the liquid crystal display includes an insulating substrate, and a gate line assembly and a storage capacitor line assembly formed on the insulating substrate. The gate line assembly has gate lines and gate electrodes. A gate insulating layer covers the gate line assembly and the storage capacitor line assembly. A semiconductor pattern is formed on the gate insulating layer. A data line assembly and storage capacitor conductive patterns are formed on the gate insulating layer overlaid with the semiconductor pattern. The data line assembly has data lines, source electrodes and drain electrodes. The storage capacitor conductive patterns are partially overlapped with the storage capacitor line assembly to thereby form first storage capacitors. A passivation layer covers the data line assembly, the storage capacitor conductive patterns and the semiconductor pattern. First and second contact holes are formed at the passivation layer while exposing the drain electrodes and the storage capacitor conductive patterns. Pixel electrodes are formed on the passivation layer while being connected to the drain electrodes and the storage capacitor conductive patterns through the first and the second contact holes. The pixel electrodes form second storage capacitors in association with parts of the storage capacitor line assembly.

BACKGROUND OF THE INVENTION

[0001] (a) Field of the Invention

[0002] The present invention relates to a thin film transistor arraypanel for a liquid crystal display, and a method for manufacturing thesame.

[0003] (b) Description of the Related Art

[0004] Generally, a liquid crystal display has two substrates withelectrodes, and a liquid crystal layer sandwiched between the twosubstrates. Voltages are applied to the electrodes so that the liquidcrystal molecules in the liquid crystal layer are re-oriented to therebycontrol the light transmission. The electrodes may be all formed at oneof the substrates. One of the substrates is called the “thin filmtransistor array panel”, and the other is called the “color filtersubstrate.”

[0005] The thin film transistor array panel has a plurality of gatelines, data lines crossing over the gate lines while defining pixelregions, thin film transistors formed at the respective pixel regionswhile being electrically connected to the gate and the data lines, andpixel electrodes electrically connected to the thin film transistors.

[0006] Storage capacitors are formed at the thin film transistor arraypanel to keep the voltage applied to the liquid crystal disposed betweenthe two substrates in a stable manner. For that purpose, a storagecapacitor line assembly is formed at the same layer as the gate linessuch that it is overlapped with the pixel electrodes to thereby formstorage capacitors. Meanwhile, the electrostatic capacitance of thestorage capacitors should be increased to enhance the brightness of thedisplay device or to make rapid response speed thereof. In thisconnection, it is necessary to enlarge the area of the storage capacitorline assembly, but this causes decreased aperture or opening ratio.

SUMMARY OF THE INVENTION

[0007] It is an object of the present invention to provide a thin filmtransistor array panel for a liquid crystal display which involvesstorage capacitors with increased electrostatic capacitance whilebearing a reasonable aperture ratio.

[0008] This and other objects may be achieved by a thin film transistorarray panel for a liquid crystal display where the storage capacitorline assembly is formed at the same layer as the data lines, or thethickness of the insulating layer for the storage capacitors isminimized.

[0009] According to one aspect of the present invention, the thin filmtransistor array panel includes an insulating substrate, and a gate lineassembly formed on the insulating substrate and including gate lines,and gate electrodes. A gate insulating layer covers the gate lineassembly. A semiconductor pattern is formed on the gate insulatinglayer. A data line assembly is formed on the gate insulating layeroverlaid with the semiconductor pattern. The data line assembly has datalines crossing over the gate lines, source electrodes connected to thedata lines and the semiconductor pattern, and drain electrodes facingthe source electrodes and connected to the semiconductor pattern.Storage capacitor electrode lines are formed between the neighboringdata lines while crossing over the gate lines. A passivation layercovers the data line assembly, the storage capacitor electrode lines andthe semiconductor pattern while bearing contact holes exposing the drainelectrodes. Pixel electrodes are formed on the passivation layer whilebeing connected to the drain electrodes through the contact holes. Thepixel electrodes are overlapped with the storage capacitor electrodelines.

[0010] The thin film transistor array panel may further include a commoninterconnection line commonly interconnecting the storage capacitorelectrode lines. The common interconnection line may be formed with thesame material as the pixel electrodes or the gate lines while crossingover the data lines in an insulated manner.

[0011] The passivation layer has a plurality of contact holes exposingthe storage capacitor electrode lines, and the common interconnectionline is connected to the storage capacitor electrode lines through thecontact holes. A subsidiary interconnection line may be connected to thestorage capacitor electrode lines. The storage capacitor electrode linesand the subsidiary interconnection line are formed with the samematerial.

[0012] Gate pads are formed at one-sided end portions of the gate lines,and data pads are formed at one-sided end portions of the data lines.First contact holes are formed at the passivation layer and the gateinsulating layer while exposing the gate pads, and second contact holesare formed at the passivation layer while exposing the data pads.Subsidiary gate and data pads are connected to the gate and the datapads through the first and the second contact holes.

[0013] In addition to the above-structured thin film transistor arraypanel, the liquid crystal display includes a counter substrate facingthe thin film transistor array panel, and a liquid crystal layersandwiched between the thin film transistor array panel and the counterpanel. The liquid crystal display has storage capacitors with anelectrostatic capacitance greater than the electrostatic capacitance ofthe liquid crystal capacitor having the liquid crystal layer by 90% ormore.

[0014] According to another aspect of the present invention, the thinfilm transistor array panel includes an insulating substrate, and a gateline assembly and a storage capacitor line assembly formed on theinsulating substrate. The gate line assembly has gate lines and gateelectrodes. A gate insulating layer covers the gate line assembly andthe storage capacitor line assembly. A semiconductor pattern is formedon the gate insulating layer. A data line assembly and storage capacitorconductive patterns are formed on the gate insulating layer overlaidwith the semiconductor pattern. The data line assembly has data lines,source electrodes and drain electrodes. The storage capacitor conductivepatterns are partially overlapped with the storage capacitor lineassembly to thereby form first storage capacitors. A passivation layercovers the data line assembly, the storage capacitor conductive patternsand the semiconductor pattern. First and second contact holes are formedat the passivation layer while exposing the drain electrodes and thestorage capacitor conductive patterns, respectively. Pixel electrodesare formed on the passivation layer while being connected to the drainelectrodes and the storage capacitor conductive patterns through thefirst and the second contact holes. The pixel electrodes form secondstorage capacitors in association with parts of the storage capacitorline assembly.

[0015] The storage capacitor line assembly has storage capacitorelectrode lines proceeding parallel to the gate lines, and storagecapacitor electrode patterns connected to the storage capacitorelectrode lines. The storage capacitor electrode patterns are overlappedwith the storage capacitor conductive patterns to thereby form the firststorage capacitors, and the storage capacitor electrode lines areoverlapped with the pixel electrodes to thereby form the second storagecapacitors.

[0016] The storage capacitor electrode patterns are formed within pixelregions defined by the gate lines and the data lines. The storagecapacitor electrode patterns are formed with a bar shape along the datalines while being overlapped with peripheral portions of the pixelelectrodes.

[0017] In addition to the above-structured thin film transistor arraypanel, the liquid crystal display includes a counter substrate facingthe thin film transistor array panel, and a liquid crystal layersandwiched between the thin film transistor array panel and the counterpanel. The first and the second storage capacitors have an electrostaticcapacitance greater than the electrostatic capacitance of the liquidcrystal layer by 90% or more.

[0018] According to still another aspect of the present invention, thethin film transistor array panel includes an insulating substrate, and agate line assembly formed on the insulating substrate. The gate lineassembly has first gate lines, gate electrodes connected to the firstgate lines, and second gate lines spaced apart from the first gate lineswith a predetermined distance. A gate insulating layer covers the gateline assembly. A semiconductor pattern is formed on the gate insulatinglayer while being overlapped with the gate electrodes. A data lineassembly and storage capacitor conductive patterns are formed on thegate insulating layer overlaid with the semiconductor pattern. The dataline assembly has data lines crossing over the first and the second gatelines, source electrodes and drain electrodes. The storage capacitorconductive patterns are partially overlapped with the second gate linesto thereby form first storage capacitors. A passivation layer covers thedata line assembly, the storage capacitor conductive patterns and thesemiconductor pattern. First and second contact holes are formed at thepassivation layer while exposing the drain electrodes and the storagecapacitor conductive patterns, respectively. Pixel electrodes are formedat the passivation layer while being connected to the drain electrodesand the storage capacitor conductive patterns through the first and thesecond contact holes. The pixel electrodes are partially overlapped withthe second gate lines to thereby form second storage capacitors.

[0019] In addition to the above-structured thin film transistor arraypanel, the liquid crystal display includes a counter substrate facingthe thin film transistor array panel, and a liquid crystal layersandwiched between the thin film transistor array panel and the counterpanel. The first and the second storage capacitors have an electrostaticcapacitance greater than the electrostatic capacitance of the liquidcrystal layer by 90% or more.

[0020] According to still another aspect of the present invention, thethin film transistor array panel includes an insulating substrate, and agate line assembly and storage capacitor electrode lines formed on theinsulating substrate. The gate line assembly has gate lines and gateelectrodes. A gate insulating layer covers the gate line assembly andthe storage capacitor electrode lines. First contact holes are formed atthe gate insulating layer while exposing the storage capacitor electrodelines. A semiconductor pattern is formed on the gate insulating layerwhile being overlapped with the gate electrodes. A data line assemblyand storage capacitor conductive patterns are formed on the gateinsulating layer overlaid with the semiconductor pattern. The data lineassembly has data lines, source electrodes and drain electrodes. Thestorage capacitor conductive patterns are connected to the storagecapacitor electrode lines through the first contact holes. A passivationlayer covers the data line assembly, the storage capacitor conductivepatterns and the semiconductor pattern. Second contact holes are formedat the passivation layer while exposing the drain electrodes. Pixelelectrodes are formed at the passivation layer while being connected tothe drain electrodes through the second contact holes. The pixelelectrodes are overlapped with the storage capacitor conductive patternsto thereby form first storage capacitors while being partiallyoverlapped with the storage capacitor electrode lines to thereby formsecond storage capacitors.

[0021] The storage capacitor electrode lines proceed parallel to thegate lines, and the storage capacitor conductive patterns are overlappedwith the storage capacitor electrode lines. The storage capacitorconductive patterns are formed within pixel regions defined by the gatelines and the data lines. The storage capacitor electrode patterns areformed with a bar shape along the data lines while being overlapped withperipheral portions of the pixel electrodes.

[0022] In addition to the above-structured thin film transistor arraypanel, the liquid crystal display includes a counter substrate facingthe thin film transistor array panel, and a liquid crystal layersandwiched between the thin film transistor array panel and the counterpanel. The first and the second storage capacitors have an electrostaticcapacitance greater than the electrostatic capacitance of the liquidcrystal layer by 90% or more.

[0023] According to still another aspect of the present invention, thethin film transistor array panel includes an insulating substrate, and agate line assembly formed on the insulating substrate. The gate lineassembly has first gate lines, gate electrodes connected to the firstgate lines, and second gate lines spaced apart from the first gate lineswith a predetermined distance. A gate insulating layer covers the gateline assembly. First contact holes are formed at the gate insulatinglayer while partially exposing the second gate lines. A semiconductorpattern is formed on the gate insulating layer while being overlappedwith the gate electrodes. A data line assembly and storage capacitorconductive patterns are formed on the gate insulating layer overlaidwith the semiconductor pattern. The data line assembly has data linescrossing over the first and the second gate lines, source electrodes anddrain electrodes. The storage capacitor conductive patterns areconnected to the second gate lines through the first contact holes. Apassivation layer covers the data line assembly, the storage capacitorconductive patterns and the semiconductor pattern. Second contact holesare formed at the passivation layer while exposing the drain electrodes.Pixel electrodes are formed at the passivation layer while beingconnected to the drain electrodes through the second contact holes. Thepixel electrodes are overlapped with the storage capacitor conductivepatterns to thereby form first storage capacitors while being partiallyoverlapped with the second gate lines to thereby form second storagecapacitors.

[0024] In addition to the above-structured thin film transistor arraypanel, the liquid crystal display includes a counter substrate facingthe thin film transistor array panel, and a liquid crystal layersandwiched between the thin film transistor array panel and the counterpanel. The first and the second storage capacitors have an electrostaticcapacitance greater than the electrostatic capacitance of the liquidcrystal layer by 90% or more.

[0025] According to still another aspect of the present invention, in amethod of fabricating a thin film transistor array panel, a gate lineassembly and a storage capacitor line assembly are formed on aninsulating substrate such that the gate line assembly has gate lines andgate electrodes. A gate insulating layer is formed on the substrate suchthat it covers the gate line assembly and the storage capacitor lineassembly. A semiconductor pattern is formed on the gate insulatinglayer. A data line assembly and storage capacitor conductive patternsare formed on the gate insulating layer overlaid with the semiconductorpattern such that the data line assembly has data lines, sourceelectrodes and drain electrodes, and the storage capacitor conductivepatterns are partially overlapped with the storage capacitor lineassembly to thereby form first storage capacitors. A passivation layeris formed on the substrate such that it covers the data line assembly,the storage capacitor conductive patterns and the semiconductor pattern.First and second contact holes are formed at the passivation layer suchthat they expose the drain electrodes and the storage capacitorconductive patterns, respectively. Pixel electrodes are formed on thepassivation layer such that they are connected to the drain electrodesand the storage capacitor conductive patterns through the first and thesecond contact holes while forming second storage capacitors inassociation with parts of the storage capacitor lines assembly.

[0026] The storage capacitor line assembly has storage capacitorelectrode lines proceeding parallel to the gate lines, and storagecapacitor electrode patterns connected to the storage capacitorelectrode lines.

[0027] According to still another aspect of the present invention, in amethod of fabricating a thin film transistor array panel, a gate lineassembly is formed on an insulating substrate such that it has firstgate lines, gate electrodes connected to the first gate lines, andsecond gate lines spaced apart from the first gate lines with apredetermined distance while proceeding parallel to the first gatelines. A gate insulating layer is formed on the substrate such that itcovers the gate line assembly. A semiconductor pattern is formed on thegate insulating layer such that it is overlapped with the gateelectrodes. A data line assembly and storage capacitor conductivepatterns are formed on the gate insulating layer overlaid with thesemiconductor pattern such that the data line assembly has data linescrossing over the first and the second gate lines, source electrodes anddrain electrodes, and the storage capacitor conductive patterns arepartially overlapped with the second gate lines to thereby form firststorage capacitors. A passivation layer is formed on the substrate suchthat it covers the data line assembly, the storage capacitor conductivepatterns and the semiconductor pattern. First and second contact holesare formed at the passivation layer such that the first and the secondcontact holes expose the drain electrodes and the storage capacitorconductive patterns, respectively. Pixel electrodes are formed on thepassivation layer such that they are connected to the drain electrodesand the storage capacitor conductive patterns through the first and thesecond contact holes while forming second storage capacitors inassociation with parts of the second gate lines.

[0028] According to still another aspect of the present invention, in amethod of fabricating a thin film transistor array panel, a gate lineassembly and storage capacitor electrode lines are formed on aninsulating substrate such that the gate line assembly has gate lines andgate electrodes. A gate insulating layer is formed on the substrate suchthat it covers the gate line assembly and the storage capacitorelectrode lines. First contact holes are formed at the gate insulatinglayer such that they expose the storage capacitor electrode lines. Asemiconductor pattern is formed on the gate insulating layer such thatit is overlapped with the gate electrodes. A data line assembly andstorage capacitor conductive patterns are formed on the gate insulatinglayer overlaid with the semiconductor pattern such that the data lineassembly has data lines, source electrodes and drain electrodes, and thestorage capacitor conductive patterns are connected to the storagecapacitor electrode lines through the first contact holes. A passivationlayer is formed on the substrate such that it covers the data lineassembly, the storage capacitor conductive patterns and thesemiconductor pattern. Second contact holes are formed at thepassivation layer such that they expose the drain electrodes. Pixelelectrodes are formed on the passivation layer such that they areconnected to the drain electrodes through the second contact holes. Thepixel electrodes are overlapped with the storage capacitor conductivepatterns to thereby form first storage capacitors while being partiallyoverlapped with the storage capacitor electrode lines to thereby formsecond storage capacitors.

[0029] According to still another aspect of the present invention, in amethod of fabricating a thin film transistor array panel, a gate lineassembly is formed on an insulating substrate such that it has firstgate lines, gate electrodes connected to the first gate lines, andsecond gate lines spaced apart from the first gate lines with apredetermined distance while proceeding parallel to the first gatelines. A gate insulating layer is formed on the substrate such that itcovers the gate line assembly. First contact holes are formed at thegate insulating layer such that they partially expose the second gatelines. A semiconductor pattern is formed on the gate insulating layersuch that it is overlapped with the gate electrodes. A data lineassembly and storage capacitor conductive patterns are formed on thegate insulating layer overlaid with the semiconductor pattern such thatthe data line assembly has data lines crossing over the first and thesecond gate lines, source electrodes and drain electrodes, and thestorage capacitor conductive patterns are connected to the second gatelines through the first contact holes. A passivation layer is formed onthe substrate such that it covers the data line assembly, the storagecapacitor conductive patterns and the semiconductor pattern. Secondcontact holes are formed at the passivation layer such that they exposethe drain electrodes. Pixel electrodes are formed on the passivationlayer such that they are connected to the drain electrodes through thesecond contact holes. The pixel electrodes are overlapped with thestorage capacitor conductive patterns to thereby form first storagecapacitors while being partially overlapped with the second gate linesto thereby form second storage capacitors.

BRIEF DESCRIPTION OF THE DRAWINGS

[0030] A more complete appreciation of the invention, and many of theattendant advantages thereof, will be readily apparent as the samebecomes better understood by reference to the following detaileddescription when considered in conjunction with the accompanyingdrawings in which like reference symbols indicate the same or thesimilar components, wherein:

[0031]FIG. 1 is a plan view of a thin film transistor array panelaccording to a first preferred embodiment of the present invention;

[0032]FIGS. 2 and 3 are cross sectional views of the thin filmtransistor array panel taken along the II-II′ line and the II-III′ lineof FIG. 1;

[0033]FIG. 4 illustrates the layout of gate lines, data lines andstorage capacitor electrode lines at the thin film transistor arraypanel shown in FIG. 1;

[0034]FIG. 5A illustrates the first step of fabricating the thin filmtransistor array panel shown in FIG. 1;

[0035]FIGS. 5B and 5C are cross sectional views of the thin filmtransistor array panel taken along the VB-VB′ line and the VC-VC′ lineof FIG. 5A;

[0036]FIG. 6A illustrates the step of fabricating the thin filmtransistor array panel following the step illustrated in FIG. 5A;

[0037]FIGS. 6B and 6C are cross sectional views of the thin filmtransistor array panel taken long the VIB-VIB′ line and the VIC-VIC′line of FIG. 6A;

[0038]FIG. 7A illustrates the step of fabricating the thin filmtransistor array panel following the step illustrated in FIG. 6A;

[0039]FIGS. 7B and 7C are cross sectional views of the thin filmtransistor array panel taken long the VIIB-VIIB′ line and the VIIC-VIIC′line of FIG. 7A;

[0040]FIG. 8 is a plan view of a thin film transistor array panelaccording to a second preferred embodiment of the present invention;

[0041]FIG. 9 is a cross sectional view of the thin film transistor arraypanel taken along the IX-IX′ line of FIG. 8;

[0042]FIG. 10A illustrates the first step of fabricating the thin filmtransistor array panel shown in FIG. 8;

[0043]FIG. 10B is a cross sectional view of the thin film transistorarray panel taken long the XBb-XB′ line of FIG. 10A;

[0044]FIG. 11A illustrates the step of fabricating the thin filmtransistor array panel following the step illustrated in FIG. 10A;

[0045]FIG. 11B is a cross sectional view of the thin film transistorarray panel taken long the XIB-XIB′ line of FIG. 11A;

[0046]FIG. 12A illustrates the step of fabricating the thin filmtransistor array panel following the step illustrated in FIG. 11A;

[0047]FIG. 12B is a cross sectional view of the thin film transistorarray panel taken long the XIIB-XIIB′ line of FIG. 12A;

[0048]FIG. 13A illustrates the step of fabricating the thin filmtransistor array panel following the step illustrated in FIG. 12A;

[0049]FIG. 13B is a cross sectional view of the thin film transistorarray panel taken long the XIIIB-XIIIB′ line of FIG. 13A;

[0050]FIG. 14 is a plan view of a thin film transistor array panelaccording to a third preferred embodiment of the present invention;

[0051]FIG. 15 is a cross sectional view of the thin film transistorarray panel taken along the XV-XV′ line of FIG. 14;

[0052]FIG. 16 is a plan view of a thin film transistor array panelaccording to a fourth preferred embodiment of the present invention;

[0053]FIG. 17 is a cross sectional view of the thin film transistorarray panel taken long the XVII-XVII′ line of FIG. 16;

[0054]FIG. 18 is a plan view of a thin film transistor array panelaccording to a fifth preferred embodiment of the present invention;

[0055]FIG. 19 is a cross sectional view of the thin film transistorarray panel taken long the XIX-XIX′ line of FIG. 18;

[0056]FIG. 20A illustrates the first step of fabricating the thin filmtransistor array panel shown in FIG. 18;

[0057]FIG. 20B is a cross sectional view of the thin film transistorarray panel taken long the XXB-XXB′ line of FIG. 20A;

[0058]FIG. 21A illustrates the step of fabricating the thin filmtransistor array panel following the step illustrated in FIG. 20A;

[0059]FIG. 21B is a cross sectional view of the thin film transistorarray panel taken long the XXIB-XXIB′ line of FIG. 21A;

[0060]FIG. 22A illustrates the step of fabricating the thin filmtransistor array panel following the step illustrated in FIG. 21A;

[0061]FIG. 22B is a cross sectional view of the thin film transistorarray panel taken long the XXIIB-XXIIB′ line of FIG. 22A;

[0062]FIG. 23A illustrates the step of fabricating the thin filmtransistor array panel following the step illustrated in FIG. 22A;

[0063]FIG. 23B is a cross sectional view of the thin film transistorarray panel taken long the XIIIB-XXIIIB′ line of FIG. 23A;

[0064]FIG. 24A illustrates the step of fabricating the thin filmtransistor array panel following the step illustrated in FIG. 23A;

[0065]FIG. 24B is a cross sectional view of the thin film transistorarray panel taken long the XXIVB-XXIVB′ line of FIG. 24A;

[0066]FIG. 25 is a plan view of a thin film transistor array panelaccording to a sixth preferred embodiment of the present invention;

[0067]FIG. 26 is a cross sectional view of the thin film transistorarray panel taken long the XXVI-XXVI′ line of FIG. 25;

[0068]FIG. 27 is a plan view of a thin film transistor array panelaccording to a seventh preferred embodiment of the present invention;

[0069]FIG. 28 is a cross sectional view of the thin film transistorarray panel taken long the XXVIII-XXVIII′ line of FIG. 27; and

[0070]FIG. 29 illustrates a waveform curve of the response speed in aliquid crystal display.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0071] Preferred embodiments of this invention will be explained withreference to the accompanying drawings.

[0072]FIG. 1 is a plan view of a thin film transistor array panel for aliquid crystal display according to a first preferred embodiment of thepresent invention, and FIGS. 2 and 3 are cross sectional views of thethin film transistor array panel taken along the II-II′ line and theIII-III′ line of FIG. 1.

[0073] A gate line assembly is formed on an insulating substrate 10 witha conductive material such as aluminum, aluminum alloy, chrome, chromealloy, molybdenum, molybdenum alloy, chrome nitride, and molybdenumnitride while bearing a thickness of 1000-3500 Å. The gate line assemblyincludes gate lines 22 proceeding in the horizontal direction, gate pads24 connected to the one-sided ends of the gate lines 22 whileelectrically contacting external driving circuits (not shown), and gateelectrodes 26 being parts of the gate lines 22 while forming thin filmtransistors with other electrode components.

[0074] The gate line assembly may have a multiple-layered structurewhere one layer is formed with a low resistance metallic material, andthe other layer with a material bearing a good contact characteristicwith other materials.

[0075] A gate insulating layer 30 with a thickness of 2,500-4,500 Å isformed on the insulating substrate 10 with silicon nitride or siliconoxide while covering the gate line assembly.

[0076] A semiconductor pattern 42 with a thickness of 800-1500 Å isformed on the gate insulating layer 30 with amorphous silicon whilebeing overlapped with the gate electrodes 26. Ohmic contact patterns 55and 56 with a thickness of 500-800 Å are formed on the semiconductorpattern 42 with amorphous silicon where n type impurities are doped athigh concentration.

[0077] A data line assembly and storage capacitor electrode lines 69 areformed on the ohmic contact patterns 55 and 56, and the gate insulatinglayer 30 with a conductive material such as aluminum, aluminum alloy,chrome, chrome alloy, molybdenum, molybdenum alloy, chrome nitride andmolybdenum nitride while bearing a thickness of 500-3500 Å. The dataline assembly includes data lines 62 proceeding in the verticaldirection while crossing over the gate lines 22 to define pixel regions,data pads 64 connected to the one-sided ends of the data lines 62 whileelectrically contacting external driving circuits, source electrodes 65connected to the data lines 62 while being extended over the ohmiccontact pattern 55, and drain electrodes 66 facing the source electrodes65 while being placed over the other ohmic contact pattern 56. The drainelectrodes 66 are extended over the gate insulating layer 30 within thepixel regions.

[0078] The storage capacity electrode lines 69 are placed at the sameplane as the data line assembly while proceeding in the verticaldirection such that they are alternately arranged with the data lines62. The storage capacity electrode lines 69 are overlapped with pixelelectrodes 82 to thereby form storage capacitors.

[0079] The data line assembly may have a multiple-layered structurewhere at least one layer is formed with a low resistance metallicmaterial.

[0080] A passivation layer 70 covers the data line assembly, the storagecapacitor electrode lines 69 and the semiconductor pattern 42 whilebearing a thickness of 500-2000 Å. The passivation layer 70 is formedwith an insulating material such as silicon nitride and silicon oxide.

[0081] First and second contact holes 72 and 74 are formed at thepassivation layer 70 while exposing the drain electrodes 66 and the datapads 64. Third contact holes 76 are formed at the passivation layer 70while exposing the gate pads 24 together with the gate insulating layer30. Furthermore, fourth contact holes 79 are formed at the passivationlayer 70 while exposing the end portions of the storage capacitorelectrode lines 69 sided with the data pads 64.

[0082] Pixel electrodes 82 are formed on the passivation layer 70 toreceive picture signals and generate electric fields together with acommon electrode (not shown) of the counter panel. The pixel electrodes82 are electrically connected to the drain electrodes 66 through thefirst contact holes 72.

[0083] The pixel electrodes 82 are overlapped with the storage capacitorelectrode lines 69 while interposing the passivation layer 70 to therebyform storage capacitors. As the passivation layer 70 disposed betweenthe pixel electrodes 82 and the storage capacitor electrode lines 69bears a thin thickness, the resulting storage capacitors bear a greatelectrostatic capacitance even when the storage capacitor electrodelines 69 bear a narrow width.

[0084] Subsidiary data pads 84 and subsidiary gate pads 86 are formed onthe passivation layer 70 while being connected to the data pads 64 andthe gate pads 24 through the second and the third contact holes 74 and76. Furthermore, a common interconnection line 88 is formed external tothe display area while proceeding parallel to the gate lines 22. Thedisplay area refers to the sum of the pixel regions. The commoninterconnection line 88 interconnects all of the storage capacitorelectrode lines 69 through the fourth contact holes 79.

[0085] The pixel electrodes 82, the subsidiary data pads 84, thesubsidiary gate pads 86 and the common interconnection line 88 areformed at the same plane with a transparent conductive material such asITO and IZO.

[0086] The common interconnection line 88 may be formed with the samematerial as the gate line assembly during the process of forming thegate line assembly. In this case, a plurality of contact holes areformed at the gate insulating layer 30 while exposing the commoninterconnection line 88. The plurality of storage capacitor electrodelines 69 contact the common interconnection line 88 through the contactholes formed at the gate insulating layer 30.

[0087]FIG. 4 illustrates the arrangement of the gate lines, the datalines and the storage capacitor electrode lines at the thin filmtransistor array panel shown in FIG. 1.

[0088] As shown in FIG. 4, the plurality of gate lines 22 proceed in thehorizontal direction parallel to each other, and the plurality of datalines 62 proceed in the vertical direction parallel to each other. Thedata lines 62 cross over the gate lines 22 while defining the pixelregions. The display area 110 refers to the sum of the pixel regions.

[0089] The one-sided end portions of the data lines 62 being the datapads are electrically connected to data driving circuits 300 to receivedata signals from them. Similarly, the one-sided end portions of thegate lines 22 being the gate pads are electrically connected to gatedriving circuits (not shown) to receive gate signals from them.

[0090] The storage capacitor electrode lines 69 are alternately arrangedwith the data lines 62. The storage capacitor electrode lines 69 areconnected to each other by way of a subsidiary interconnection line 61placed external to the display area 110. It is preferable that thestorage capacitor electrode lines 69 and the subsidiary interconnectionline 61 are formed with the same material while being commonlyinterconnected.

[0091] The common interconnection line 88 is placed at the ends of thestorage capacitor electrode lines 69 sided with the data drivingcircuits while interconnecting all of the storage capacitor electrodelines 69. It is preferable that the common interconnection line 88 isformed with the same material as the pixel electrodes 82 or the gateline assembly. This is to prevent the common interconnection line 88from being short circuited with the portions of the data lines 62connected to the data driving circuits 300 external to the display area110.

[0092] The storage capacitor electrode lines 69 are electricallyconnected to the data driving circuits 300 to receive common electrodevoltages from them.

[0093] A method of fabricating the thin film transistor array panel willbe now explained with reference to FIGS. 5A to 7C as well as FIGS. 1 to4.

[0094] As shown in FIGS. 5A to 5C, a gate line assembly layer isdeposited onto an insulating substrate 10, and patterned throughphotolithography to thereby form a gate line assembly. The gate lineassembly includes gate lines 22, gate pads 24, and gate electrodes 26.

[0095] Thereafter, a gate insulating layer 30 based on an insulatingmaterial such as silicon nitride is deposited onto the insulatingsubstrate 10 such that it covers the gate line assembly.

[0096] An amorphous silicon layer and a conductive type impurities-dopedamorphous silicon layer are sequentially deposited onto the gateinsulating layer 30, and patterned through photolithography to therebyform a semiconductor pattern 42 and an ohmic contact pattern 52.

[0097] As shown in FIGS. 6A to 6C, a metallic layer is deposited ontothe entire surface of the substrate, and patterned throughphotolithography to thereby form a data line assembly and storagecapacitor electrode lines 69. The data line assembly includes data lines62, data pads 64, source electrodes 65, and drain electrodes 66. Thestorage capacitor electrode lines 69 are alternately arranged with thedata lines 62.

[0098] The ohmic contact pattern 52 is etched using the source electrode65 and the drain electrode 66 as a mask to thereby separate it into afirst portion 55 contacting the source electrode 65, and a secondportion 56 contacting the drain electrode 66.

[0099] As shown in FIGS. 7A to 7C, a passivation layer 70 covers thedata line assembly, the storage capacitor electrode lines 69, and thesemiconductor pattern 42. The passivation layer 70 is formed withsilicon nitride while bearing a thin thickness. In consideration of theelectrostatic capacitance of the storage capacitors to be formed, it ispreferable that the thickness of the passivation layer 70 is controlledin an appropriate manner.

[0100] The passivation layer 70 and the gate insulating layer 30 arepatterned through photolithography to thereby form first to fourthcontact holes 72, 74, 76 and 79.

[0101] As shown in FIGS. 1 to 3, a transparent conductive layer based onITO or IZO is deposited onto the entire surface of the substrate 10.

[0102] The transparent conductive layer is patterned throughphotolithography to thereby form pixel electrodes 82, subsidiary datapads 84, subsidiary gate pads 86, and a common interconnection line 88.The pixel electrodes 82 are connected to the drain electrodes 66 throughthe first contact holes 72. The subsidiary data and gate pads 84 and 86are connected to the data and gate pads 64 and 24 through the second andthe third contact holes 74 and 76. The common interconnection line 88interconnects all of the storage capacitor electrode lines 69 throughthe fourth contact holes 79.

[0103] The common interconnection line 88 may be formed with the samematerial as the gate line assembly. For that purpose, the commoninterconnection line is formed during the process of forming the gateline assembly while being followed by the formation of the gateinsulating layer 30. A plurality of contact holes exposing the commoninterconnection line are then formed at the gate insulating layer 30.The storage capacitor electrode lines 69 are formed during the processof forming the data line assembly. In this process, the storagecapacitor electrode lines 69 are connected to the common interconnectionline through the contact holes.

[0104] As described above, the storage capacitor electrode lines areformed at the same plane as the data lines such that they are overlappedwith the pixel electrodes while interposing the passivation layerbearing a thin thickness to thereby form storage capacitors.

[0105] Alternatively, the storage capacitors may be formed using a gateinsulating layer instead of the passivation layer.

[0106]FIG. 8 is a plan view of a thin film transistor array panelaccording to a second preferred embodiment of the present invention, andFIG. 9 is a cross sectional view of the thin film transistor array paneltaken along the IX-IX′ line of FIG. 8.

[0107] A gate line assembly and a storage capacitor line assembly areformed on an insulating substrate 10 with a conductive material such asaluminum, aluminum alloy, chrome, chrome alloy, molybdenum, molybdenumalloy, chrome nitride, and molybdenum nitride while bearing a thicknessof 1000-3500 Å.

[0108] The gate line assembly includes gate lines 22 proceeding in thehorizontal direction, gate pads 24 formed at the one-sided end portionsof the gate lines 22 while electrically contacting external drivingcircuits (not shown), and gate electrodes 26 being parts of the gatelines 22 while forming thin film transistors with other components.

[0109] The storage capacitor line assembly includes rectangular-shapedstorage capacitor electrode patterns 28 disposed between the neighboringgate lines 22, and storage capacitor electrode lines 29 connected to thestorage capacitor electrode patterns in the neighboring pixel regionswhile proceeding in the horizontal direction parallel to the gate lines22.

[0110] The gate line assembly and the storage capacitor line assemblymay have a multiple-layered structure where at least one layer is formedwith a low resistance metallic material.

[0111] A gate insulating layer 30 with a thickness of 2500-4500 Å isformed on the insulating substrate 10 with silicon nitride or siliconoxide while covering the gate line assembly and the storage capacitorline assembly.

[0112] A semiconductor pattern 42 with a thickness of 800-1500 Å isformed on the gate insulating layer 30 with amorphous silicon whilebeing overlapped with the gate electrodes 26. Ohmic contact patterns 55and 56 with a thickness of 500-800 Å are formed on the semiconductorpattern 42 with amorphous silicon where n type impurities are doped athigh concentration.

[0113] A data line assembly and storage capacitor conductive patterns 68are formed on the ohmic contact patterns 55 and 56 and the gateinsulating layer 30 with a conductive material such as aluminum,aluminum alloy, chrome, chrome alloy, molybdenum, molybdenum alloy,chrome nitride and molybdenum nitride while bearing a thickness of500-3500 Å.

[0114] The data line assembly includes data lines 62 proceeding in thevertical direction while crossing over the gate lines 22 to define pixelregions, data pads 64 formed at the one-sided end portions of the datalines 62 while electrically contacting external driving circuits, sourceelectrodes 65 connected to the data lines 62 while being extended overthe ohmic contact pattern 55, and drain electrodes 66 facing the sourceelectrodes 65 while being placed over the other ohmic contact pattern56. The drain electrodes 66 are extended over the gate insulating layer30 within the pixel regions.

[0115] The storage capacity conductive patterns 68 are placed at thesame plane as the data line assembly while bearing an island shape suchthat they are overlapped with the storage capacitor electrode patterns28 while interposing the gate insulating layer 30 to thereby formstorage capacitors. The storage capacitor conductive patterns 68 areelectrically connected to pixel electrodes 82 to be described later toreceive picture signal voltages.

[0116] The data line assembly and the storage capacitor conductivepatterns 68 may have a multiple-layered structure where at least onelayer is formed with a low resistance metallic material.

[0117] A passivation layer 70 covers the data line assembly, the storagecapacitor conductive patterns 68 and the semiconductor pattern 42 whilebearing a thickness of 500-2000 Å. The passivation layer 70 is formedwith an insulating material such as silicon nitride and silicon oxide.

[0118] First and second contact holes 72 and 74 are formed at thepassivation layer 70 while exposing the drain electrodes 66 and the datapads 64. Third contact holes 76 are formed at the passivation layer 70while exposing the gate pads 24 together with the gate insulating layer30. Furthermore, fourth contact holes 78 are formed at the passivationlayer 70 while exposing the storage capacitor conductive patterns 68.

[0119] Pixel electrodes 82 are formed on the passivation layer 70 suchthat they are electrically connected to the drain electrodes 66 and thestorage capacitor conductive patterns 68 through the first and thefourth contact holes 72 and 78.

[0120] Subsidiary data pads 84 and subsidiary gate pads 86 are formed onthe passivation layer 70 while being connected to the data pads 64 andthe gate pads 24 through the second and the third contact holes 74 and76.

[0121] The pixel electrodes 82, the subsidiary data pads 84 and thesubsidiary gate pads 86 are formed with a transparent conductivematerial such as ITO and IZO.

[0122] The pixel electrodes 82 are overlapped with the storage capacitorline assembly while interposing the passivation layer 70 and the gateinsulating layer 30 to thereby form storage capacitors.

[0123] The pixel electrodes 82 are connected to the storage capacitorconductive patterns 68. In this way, the storage capacitor conductivepatterns 68 form other storage capacitors in association with thestorage capacitor electrode patterns 28 while interposing the gateinsulating layer 30. In this case, as the thickness of the gateinsulating layer 30 disposed between the storage capacitor conductivepatterns 68 and the storage capacitor electrode patterns 28 is small,the electrostatic capacitance of the resulting storage capacitorsbecomes increased even with the same overlapping area compared to theoverlapping of the storage capacitor electrode patterns 28 and the pixelelectrodes 82. Consequently, the aperture ratio with respect to thestorage capacity becomes enhanced.

[0124] A method of fabricating the thin film transistor array panel willbe now explained with reference to FIGS. 10A to 13B as well as FIGS. 8and 9.

[0125] As shown in FIGS. 10A and 10B, a metallic layer is deposited ontoan insulating substrate 10, and patterned through photolithography tothereby form a gate line assembly and a storage capacitor line assembly.The gate line assembly includes gate lines 22, gate pads 24, and gateelectrodes 26. The storage capacitor line assembly includes storagecapacitor electrode patterns 28, and storage capacitor electrode lines29.

[0126] Thereafter, as shown in FIGS. 11A and 11B, a gate insulatinglayer 30 based on an insulating material such as silicon nitride isdeposited onto the insulating substrate 10 such that it covers the gateline assembly and the storage capacitor line assembly.

[0127] An amorphous silicon layer and a conductive type impurities-dopedamorphous silicon layer are sequentially deposited onto the gateinsulating layer 30, and patterned through photolithography to therebyform a semiconductor pattern 42 and an ohmic contact pattern 52.

[0128] As shown in FIGS. 12A and 12B, a metallic layer is deposited ontothe entire surface of the substrate 10, and patterned throughphotolithography to thereby form a data line assembly, and storagecapacitor conductive patterns 68. The data line assembly includes datalines 62, data pads 64, source electrodes 65, and drain electrodes 66.The storage capacitor conductive patterns 68 are overlapped with thestorage capacitor electrode patterns 28.

[0129] The ohmic contact pattern 52 is etched using the source electrode65 and the drain electrode 66 as a mask to thereby separate it into afirst portion 55 contacting the source electrode 65, and a secondportion 56 contacting the drain electrode 66.

[0130] As shown in FIGS. 13A and 13B, a passivation layer 70 is formedon the entire surface of the substrate 10 having the data line assembly,the storage capacitor conductive patterns 68 and the semiconductorpattern 42 with silicon nitride or silicon oxide. The passivation layer70 and the gate insulating layer 30 are patterned throughphotolithography to thereby form first to fourth contact holes 72, 74,76 and 78. The first contact holes 72, the second contact holes 74 andthe fourth contact holes 78 are formed at the passivation layer 70 whileexposing the drain electrodes 66, the data pads 64 and the storagecapacitor conductive patterns 68, respectively. Furthermore, the thirdcontact holes 76 are formed at the passivation layer 70 and the gateinsulating layer 30 while exposing the gate pads 24.

[0131] As shown in FIGS. 8 and 9, a transparent conductive layer basedon ITO or IZO is deposited onto the entire surface of the substrate 10.

[0132] The transparent conductive layer is patterned throughphotolithography to thereby form pixel electrodes 82, subsidiary datapads 84, and subsidiary gate pads 86. The pixel electrodes 82 areconnected to the drain electrodes 66 and the storage capacitorconductive patterns 68 through the first and the fourth contact holes 72and 78. The subsidiary data and gate pads 84 and 86 are connected to thedata and gate pads 64 and 24 through the second and the third contactholes 74 and 76.

[0133] In this preferred embodiment, the storage capacitor conductivepatterns 68 are placed at the pixel regions between the neighboring gatelines while bearing an island shape. Alternatively, the storagecapacitor conductive patterns 68 may be formed at the periphery of thepixel regions while bearing a bar shape. In this case, the storagecapacitor electrode patterns 28 for forming storage capacitors inassociation with the storage capacitor conductive patterns 68 are alsoformed with a bar shape.

[0134]FIG. 14 is a plan view of a thin film transistor array panelaccording to a third preferred embodiment of the present invention, andFIG. 15 is a cross sectional view of the thin film transistor arraypanel taken along the XV-XV′ line of FIG. 14.

[0135] In this preferred embodiment, the storage capacitor electrodepatterns 28 are placed at both peripheral sides of the pixel regionswhile bearing a bar shape. Of course, the respective storage capacitorelectrode patterns 28 are connected to the storage capacitor electrodelines 29.

[0136] The storage capacitor conductive patterns 68 for forming storagecapacitors in association with the storage capacitor electrode patterns28 are overlapped with the storage capacitor electrode patterns 28 whileinterposing the gate insulating layer 30.

[0137] The fourth contact holes 78 through which the storage capacitorconductive patterns 68 are connected to the pixel electrodes 82 areestablished to partially expose the storage capacitor conductivepatterns 68.

[0138] In this structure, the storage capacitor electrode lines 29 formstorage capacitors in association with the pixel electrodes 82 whileinterposing the gate insulating layer 30 and the passivation layer 70.Furthermore, the storage capacitor electrode patterns 28 form storagecapacitors in association with the storage capacitor conductive patterns68 while interposing the gate insulating layer 30.

[0139] With such a structure, the electrostatic capacitance of theresulting storage capacitors becomes increased even with the sameoverlapping area compared to the case where the storage capacitorelectrode patterns 28 are overlapped with only the pixel electrodes 82.Consequently, the aperture ratio with respect to the storage capacitybecomes enhanced.

[0140] Furthermore, as the bar-shaped storage capacitor electrodepatterns 28 or storage capacitor conductive patterns 68 are placedbetween the pixel electrodes 82 and the data lines 62, leakage of lightbetween the pixel electrodes 82 and the data lines 62 can be prevented.

[0141] In the second and third preferred embodiments of the presentinvention, the storage capacitor line assembly is formed in a separatemanner. Alternatively, parts of the gate lines may be utilized as thestorage capacitor electrodes.

[0142]FIG. 16 is a plan view of a thin film transistor array panelaccording to a fourth preferred embodiment of the present invention, andFIG. 17 is a cross sectional view of the thin film transistor arraypanel taken along the XIII-XVII′ line of FIG. 16.

[0143] In this preferred embodiment, the pixel electrodes arranged atany one gate line are overlapped with parts of the previous gate line toform storage capacitors. That is, parts of the gate lines are used toform the desired storage capacitors without forming a storage capacitorline assembly in a separate manner.

[0144] As shown in FIG. 16, the pixel electrodes 82 at the nth gate line22 (Gn) are overlapped with the (n-1)th gate line 22 (Gn-1) while beingextended in its area.

[0145] The storage capacitor conductive patterns 68 are partiallyoverlapped with the gate lines 22 while interposing the gate insulatinglayer 30. The storage capacitor conductive patterns 68 are placed at thesame plane as the data line assembly. The fourth contact holes 78exposing the storage capacitor conductive patterns 68 are formed at thepassivation layer 70, and the pixel electrodes 82 at any one gate line22 are connected to the storage capacitor conductive patterns 68 placedover the previous gate line 22 through the fourth contact holes 78.

[0146] The storage capacitor conductive patterns 68 are overlapped withthe gate lines 22 while interposing the gate insulating layer 30 tothereby form storage capacitors. The storage capacitor conductivepatterns 68 placed over the (n-1)th gate line 22 (Gn-1) receive therelevant signals from the pixel electrodes 82 at the nth gate line 22(Gn).

[0147] In the above structure, the storage capacity becomessignificantly increased compared to the case where the storagecapacitors are formed only through overlapping the pixel electrodes 82with the gate lines 22. Furthermore, as a separate storage capacitorline assembly is not needed, the aperture ratio can be further enhanced.

[0148]FIG. 18 is a plan view of a thin film transistor array panelaccording to a fifth preferred embodiment of the present invention, andFIG. 19 is a cross sectional view of the thin film transistor arraypanel taken along the XIX-XIX′ line of FIG. 18.

[0149] A gate line assembly and storage capacitor electrode lines 27 areformed on an insulating substrate 10 with a conductive material such asaluminum, aluminum alloy, chrome, chrome alloy, molybdenum, molybdenumalloy, chrome nitride, and molybdenum nitride while bearing a thicknessof 1000-3500 Å.

[0150] The gate line assembly includes gate lines 22 proceeding in thehorizontal direction, gate pads 24 formed at the one-sided end portionsof the gate lines 22 while electrically contacting external drivingcircuits (not shown), and gate electrodes 26 being parts of the gatelines 22 while forming thin film transistors with other electrodecomponents.

[0151] The storage capacitor electrode lines 27 are placed between theneighboring gate lines 22 while proceeding in the horizontal directionparallel to the gate lines 22.

[0152] The gate line assembly and the storage capacitor electrode lines27 may have a multiple-layered structure where at least one layer isformed with a low resistance metallic material.

[0153] A gate insulating layer 30 with a thickness of 2500-4500 Å isformed on the insulating substrate 10 with silicon nitride or siliconoxide while covering the gate line assembly and the storage capacitorelectrode lines 27.

[0154] First contact holes 32 are formed at the gate insulating layer 30while exposing the storage capacitor electrode lines 27.

[0155] A semiconductor pattern 42 with a thickness of 800-1500 Å isformed on the gate insulating layer 30 with amorphous silicon whilebeing overlapped with the gate electrodes 26. Ohmic contact patterns 55and 56 with a thickness of 500-800 Å are formed on the semiconductorpattern 42 with amorphous silicon where n type impurities are doped athigh concentration.

[0156] A data line assembly and storage capacitor conductive patterns 67are formed on the ohmic contact patterns 55 and 56 and the gateinsulating layer 30 with a conductive material such as aluminum,aluminum alloy, chrome, chrome alloy, molybdenum, molybdenum alloy,chrome nitride and molybdenum nitride while bearing a thickness of500-3500 Å.

[0157] The data line assembly includes data lines 62 proceeding in thevertical direction while crossing over the gate lines 22 to define pixelregions, data pads 64 connected to the one-sided ends of the data lines62 while electrically contacting external driving circuits, sourceelectrodes 65 protruded from the data lines 62 while being extended overthe ohmic contact pattern 55, and drain electrodes 66 facing the sourceelectrodes 65 while being placed over the other ohmic contact pattern56. The drain electrodes 66 are extended over the gate insulating layer30 within the pixel regions.

[0158] The storage capacity conductive patterns 67 are placed at thesame plane as the data line assembly while being connected to thestorage capacitor electrode lines 27 through the first contact holes 32.The storage capacitor conductive patterns 67 are overlapped with pixelelectrodes 82 to be described later to thereby form storage capacitors.The storage capacitor conductive patterns 67 are connected to thestorage capacitor electrode lines 27 to receive common voltages.

[0159] The data line assembly and the storage capacitor conductivepatterns 67 may have a multiple-layered structure where at least onelayer is formed with a low resistance metallic material.

[0160] A passivation layer 70 covers the data line assembly, the storagecapacitor conductive patterns 67 and the semiconductor pattern 42 whilebearing a thickness of 500-2000 Å. The passivation layer 70 is formedwith an insulating material such as silicon nitride and silicon oxide.

[0161] Second and third contact holes 72 and 74 are formed at thepassivation layer 70 while exposing the drain electrodes 66, and thedata pads 64. Fourth contact holes 76 are further formed at thepassivation layer 70 while exposing the gate pads 24 together with thegate insulating layer 30.

[0162] Pixel electrodes 82 are formed on the passivation layer 70 suchthat they are electrically connected to the drain electrodes 66 throughthe second contact holes 72.

[0163] Subsidiary data pads 84 and subsidiary gate pads 86 are formed onthe passivation layer 70 while being connected to the data pads 64 andthe gate pads 24 through the third and the fourth contact holes 74 and76.

[0164] The pixel electrodes 82, the subsidiary data pads 84 and thesubsidiary gate pads 86 are formed with a transparent conductivematerial such as ITO and IZO.

[0165] The pixel electrodes 82 are overlapped with the storage capacitorelectrode lines 27 while interposing the passivation layer 70 and thegate insulating layer 30 to thereby form storage capacitors.

[0166] The pixel electrodes 82 are also overlapped with the storagecapacitor conductive patterns 67 connected to the storage capacitorelectrode lines 27 while interposing the passivation layer 70 to therebyform other storage capacitors. In this case, as the thickness of thepassivation layer 70 disposed between the pixel electrodes 82 and thestorage capacitor conductive patterns 67 is small, the electrostaticcapacitance of the resulting storage capacitors becomes increased evenwith the same overlapping area compared to the overlapping of thestorage capacitor electrode lines 27 and the pixel electrodes 82.Consequently, the aperture ratio with respect to the storage capacitybecomes enhanced.

[0167] A method of fabricating the thin film transistor array panel willbe now explained with reference to FIGS. 20A to 24B as well as FIGS. 18and 19.

[0168] As shown in FIGS. 20A and 20B, a metallic layer is deposited ontoan insulating substrate 10, and patterned through photolithography tothereby form a gate line assembly and storage capacitor electrode lines27. The gate line assembly includes gate lines 22, gate pads 24, andgate electrodes 26.

[0169] Thereafter, as shown in FIGS. 21A and 21B, a gate insulatinglayer 30 based on an insulating material such as silicon nitride isdeposited onto the insulating substrate 10 such that it covers the gateline assembly and the storage capacitor electrode lines 27.Subsequently, an amorphous silicon layer 40 and a conductive typeimpurities-doped amorphous silicon layer 50 are sequentially depositedonto the gate insulating layer 30.

[0170] Thereafter, the amorphous silicon layer 40, the impurities-dopedamorphous silicon layer 50 and the gate insulating layer 30 arepatterned through photolithography to thereby form first contact holes32 exposing the storage capacitor electrode lines 27.

[0171] As shown in FIGS. 22A and 22B, the amorphous silicon layer 40 andthe impurities-doped amorphous silicon layer 50 are patterned throughphotolithography to thereby form a semiconductor pattern 42 and an ohmiccontact pattern 52.

[0172] As shown in FIGS. 23A and 23B, a metallic layer is deposited ontothe entire surface of the substrate 10, and patterned throughphotolithography to thereby form a data line assembly, and storagecapacitor conductive patterns 67. The data line assembly includes datalines 62, data pads 64, source electrodes 65, and drain electrodes 66.The storage capacitor conductive patterns 67 are connected to thestorage capacitor electrode lines 27 through the first contact holes 32.

[0173] The ohmic contact pattern 52 is etched using the source electrode65 and the drain electrode 66 as a mask to thereby separate it into afirst portion 55 contacting the source electrode 65, and a secondportion 56 contacting the drain electrode 66.

[0174] As shown in FIGS. 24A and 24B, a passivation layer 70 is formedon the entire surface of the substrate 10 having the data line assembly,the storage capacitor conductive patterns 67 and the semiconductorpattern 42 with silicon nitride or silicon oxide. The passivation layer70 and the gate insulating layer 30 are patterned throughphotolithography to thereby form second to fourth contact holes 72, 74and 76. The second and the third contact holes 72 and 74 are formed atthe passivation layer 70 while exposing the drain electrodes 66, and thedata pads 64. The fourth contact holes 76 are formed at the passivationlayer 70 and the gate insulating layer 30 while exposing the gate pads24.

[0175] As shown in FIGS. 18 and 19, a transparent conductive layer basedon ITO or IZO is deposited onto the entire surface of the substrate 10.

[0176] The transparent conductive layer is patterned throughphotolithography to thereby form pixel electrodes 82, subsidiary datapads 84, and subsidiary gate pads 86. The pixel electrodes 82 areconnected to the drain electrodes 66 through the second contact holes72. The subsidiary data and gate pads 84 and 86 are connected to thedata and gate pads 64 and 24 through the third and the fourth contactholes 74 and 76.

[0177] In this preferred embodiment, the storage capacitor conductivepatterns 67 are placed at the pixel regions between the neighboring gatelines. Alternatively, the storage capacitor conductive patterns 67 maybe formed at the periphery of the pixel regions while bearing a barshape.

[0178]FIG. 25 is a plan view of a thin film transistor array panelaccording to a sixth preferred embodiment of the present invention, andFIG. 26 is a cross sectional view of the thin film transistor arraypanel taken along the XXVI-XXI′ line of FIG. 25.

[0179] In this preferred embodiment, the storage capacitor conductivepatterns 67 are placed at both peripheral sides of the pixel regionswhile bearing a bar shape. The storage capacitor conductive patterns 67are connected to the storage capacitor electrode lines 27 through thefirst contact holes 32 formed at the gate insulating layer 30.

[0180] The storage capacitor electrode lines 27 form storage capacitorsin association with the pixel electrodes 82 while interposing the gateinsulating layer 30 and the passivation layer 70. Furthermore, thestorage capacitor conductive patterns 67 form other storage capacitorsin association with the pixel electrodes 82 while interposing thepassivation layer 70.

[0181] With such a structure, the electrostatic capacitance of thestorage capacitors becomes increased even with the same overlapping areacompared to the case where only the storage capacitor electrode lines 27are overlapped with the pixel electrodes 82. Consequently, the apertureratio with respect to the storage capacity becomes enhanced.

[0182] Furthermore, as the bar-shaped storage capacitor conductivepatterns 67 are placed between the pixel electrodes 82 and the datalines 62, leakage of light between the pixel electrodes 82 and the datalines 62 can be prevented.

[0183] In the fifth and sixth preferred embodiments of the presentinvention, the storage capacitor line assembly is formed in a separatemanner. Alternatively, parts of the gate lines may be utilized as thestorage capacitor electrodes.

[0184]FIG. 27 is a plan view of a thin film transistor array panelaccording to a seventh preferred embodiment of the present invention,and FIG. 28 is a cross sectional view of the thin film transistor arraypanel taken along the XXVIII-XXVIII′ line of FIG. 27.

[0185] In this preferred embodiment, the pixel electrodes arranged atany one gate line are overlapped with parts of the previous gate line toform storage capacitors. That is, parts of the gate lines are used toform the desired storage capacitors without forming a storage capacitorline assembly in a separate-manner.

[0186] As shown in FIG. 27, the pixel electrodes 82 at the nth gate line22 (Gn) are overlapped with the (n-1)th gate line 22 (Gn-1) while beingextended in its area.

[0187] The storage capacitor conductive patterns 67 are partiallyoverlapped with the gate lines 22 while interposing the gate insulatinglayer 30. The storage capacitor conductive patterns 67 are placed at thesame plane as the data line assembly. The fourth contact holes 78exposing the storage capacitor conductive patterns 67 are formed at thepassivation layer 70. The storage capacitor conductive patterns 67placed over the (n-1)th gate line 22 (Gn-1) are connected to the pixelelectrodes 82 at the nth gate line 22 (Gn).

[0188] The storage capacitor conductive patterns 67 are overlapped withthe gate lines 22 while interposing the gate insulating layer 30 tothereby form storage capacitors. The storage capacitor conductivepatterns 68 placed over the (n-1)th gate line 22 (Gn-1) receive therelevant signals from the pixel electrodes 82 at the nth gate line 22(Gn).

[0189] In the above structure, the storage capacity becomessignificantly increased compared to the case where the storagecapacitors are formed only through overlapping the pixel electrodes 82with the gate lines 22. Furthermore, as a separate storage capacitorline assembly is not needed, the aperture ratio can be further enhanced.

[0190] The inventive structure may be well adapted for use with all ofthe liquid crystal display modes. Particularly, in case such a structureis employed for use with the optically compensated birefringence (OCB)mode, various advantages are resulted.

[0191] As the Δ ε value of the liquid crystal is great with the OCB modeliquid crystal display, the difference between the dielectric constantat the initial state and the dielectric constant at the succeeding stateas a function of the gray values is also great, and therefore, variationin the liquid crystal voltage is inevitably made to a large scale.

[0192] Meanwhile, as shown in FIG. 29, the waveform (time-brightness)curve of the response speed measured with all of the liquid crystaldisplay modes bears a two-stepped waveform exhibiting two steppeddifferences.

[0193] As the response speed is measured while altering the totalbrightness from 10% to 90%, it turns out to be slower in case thebrightness at the two-stepped portion is less than 90%.

[0194] The OCB mode liquid crystal display exhibits a characteristic inthat the two-stepped waveform occurs at the first frame, and a normalbrightness is maintained at the second frame or the third frame.Therefore, in case the electrostatic capacitance at the two-steppedportion is increased to be 90% or more, particularly 95% or more, thedesired normal brightness can be maintained at the first frame, therebymaking rapid response speed.

[0195] Table 1 lists the brightness values at the two-stepped portionover the waveform (time-brightness) curve of the response speed as afunction of the ratio of the electrostatic capacitance Cst of thestorage capacitors to the electrostatic capacitance Clc of the liquidcrystal in the OCB mode liquid crystal display. TABLE 1 Clc:Cst1.00:0.70 1.00:0.91 Two-stepped portion 81.8% 87.3% (brightness %)

[0196] It can be known from Table 1 that as the storage capacity Cst isincreased, the brightness at the two-stepped portion is approximated to90%. Therefore, the rapid response speed can be obtained throughincreasing the storage capacity such that the brightness at thetwo-stepped portion goes over 90%. Particularly, in case the storagecapacity is increased such that the brightness at the two-steppedportion goes over 95%, the response speed can be further enhanced. Inorder to increase the storage capacity to such a degree, the storagecapacitors according to the first to seventh preferred embodiments maybe applied for use in the OCB mode liquid crystal display. That is, thestorage capacitor electrode lines are formed at the same plane as thedata line assembly such that they are overlapped with the pixelelectrodes while interposing only the passivation layer. In thisstructure, the storage capacity as well as the aperture ratio aresignificantly enhanced without enlarging the area of the storagecapacitor electrode lines, compared to the case where the storagecapacitor electrode lines are formed at the same plane as the gate lineassembly such that they are overlapped with the pixel electrodes whileinterposing the passivation layer and the gate insulating layer: As onlyone of the passivation layer and the gate insulating layer is disposedbetween the storage capacitor electrodes, it is not needed to enlargethe area of the storage capacitor electrode components. Consequently,the storage capacity can be increased without decreasing the apertureratio.

[0197] As described above, with the inventive structure, the storagecapacity can be increased without decreasing the aperture ratio whileenhancing the response speed.

[0198] While the present invention has been described in detail withreference to the preferred embodiments, those skilled in the art willappreciate that various modifications and substitutions can be madethereto without departing from the spirit and scope of the presentinvention as set forth in the appended claims.

what is claimed is:
 1. A thin film transistor array panel comprising: aninsulating substrate; a gate line assembly formed on the insulatingsubstrate with gate lines, and gate electrodes; a gate insulating layercovering the gate line assembly; a semiconductor pattern formed on thegate insulating layer; a data line assembly formed on the gateinsulating layer overlaid with the semiconductor pattern, the data lineassembly having data lines crossing over the gate lines, sourceelectrodes connected to the data lines, and drain electrodes facing thesource electrodes; storage capacitor electrode lines formed between theneighboring data lines while crossing over the gate lines; a passivationlayer covering the data line assembly, the storage capacitor electrodelines and the semiconductor pattern while bearing contact holes exposingthe drain electrodes; and pixel electrodes formed on the passivationlayer while being connected to the drain electrodes through the contactholes, the pixel electrodes being overlapped with the storage capacitorelectrode lines.
 2. The thin film transistor array panel of claim 1further comprising a common interconnection line commonlyinterconnecting the storage capacitor electrode lines.
 3. The thin filmtransistor array panel of claim 2 wherein the common interconnectionline is formed with the same material as the pixel electrodes whilecrossing over the data lines in an insulated manner.
 4. The thin filmtransistor array panel of claim 2 wherein the common interconnectionline is formed with the same material as the gate lines while crossingover the data lines in an insulated manner.
 5. The thin film transistorarray panel of claim 3 wherein the passivation layer has a plurality ofcontact holes exposing the storage capacitor electrode lines, and thecommon interconnection line is connected to the storage capacitorelectrode lines through the contact holes.
 6. The thin film transistorarray panel of claim 2 further comprising a subsidiary interconnectionline connected to the storage capacitor electrode lines.
 7. The thinfilm transistor array panel of claim 6 wherein the storage capacitorelectrode lines and the subsidiary interconnection line are formed withthe same material.
 8. The thin film transistor array panel of claim 1further comprising: gate pads formed at one-sided end portions of thegate lines; data pads formed at one-sided end portions of the datalines; first contact holes formed at the passivation layer and the gateinsulating layer while exposing the gate pads; second contact holesformed at the passivation layer while exposing the data pads; andsubsidiary gate and data pads connected to the gate and the data padsthrough the first and the second contact holes.
 9. A liquid crystaldisplay comprising: the thin film transistor array panel of claim 1; acounter substrate facing the thin film transistor array panel; and aliquid crystal layer sandwiched between the thin film transistor arraypanel and the counter panel.
 10. The liquid crystal display of claim 9having storage capacitors with an electrostatic capacitance greater thanthe electrostatic capacitance of the liquid crystal layer by 90% ormore.
 11. The liquid crystal display of claim 10 wherein theelectrostatic capacitance of the storage capacitors is greater than theelectrostatic capacitance of the liquid crystal layer by 95% or more.12. The liquid crystal display of claim 9 wherein the thin filmtransistor array panel further comprises a common interconnection linecommonly interconnecting the storage capacitor electrode lines.
 13. Theliquid crystal display of claim 12 wherein the common interconnectionline is formed with the same material as the pixel electrodes whilecrossing over the data lines in an insulated manner.
 14. The liquidcrystal display of claim 13 wherein the passivation layer has aplurality of contact holes exposing the storage capacitor electrodelines, and the common interconnection line is connected to the storagecapacitor electrode lines through the contact holes.
 15. The liquidcrystal display of claim 12 wherein the thin film transistor array panelfurther comprises a subsidiary interconnection line connected to thestorage capacitor electrode lines.
 16. The liquid crystal display ofclaim 15 wherein the storage capacitor electrode lines and thesubsidiary interconnection line are formed with the same material.
 17. Athin film transistor array panel comprising: an insulating substrate; agate line assembly and a storage capacitor line assembly formed on theinsulating substrate, the gate line assembly having gate lines and gateelectrodes; a gate insulating layer covering the gate line assembly andthe storage capacitor line assembly; a semiconductor pattern formed onthe gate insulating layer; a data line assembly and storage capacitorconductive patterns formed on the gate insulating layer overlaid withthe semiconductor pattern, the data line assembly having data lines,source electrodes and drain electrodes, the storage capacitor conductivepatterns being partially overlapped with the storage capacitor lineassembly to thereby form first storage capacitors; a passivation layercovering the data line assembly, the storage capacitor conductivepatterns and the semiconductor pattern; first and second contact holesformed at the passivation layer while exposing the drain electrodes andthe storage capacitor conductive patterns, respectively; and pixelelectrodes formed on the passivation layer while being connected to thedrain electrodes and the storage capacitor conductive patterns throughthe first and the second contact holes, the pixel electrodes formingsecond storage capacitors in association with parts of the storagecapacitor line assembly.
 18. The thin film transistor array panel ofclaim 17 wherein the storage capacitor line assembly has storagecapacitor electrode lines proceeding parallel to the gate lines, andstorage capacitor electrode patterns connected to the storage capacitorelectrode lines.
 19. The thin film transistor array panel of claim 18wherein the storage capacitor electrode patterns are overlapped with thestorage capacitor conductive patterns to thereby form the first storagecapacitors, and the storage capacitor electrode lines are overlappedwith the pixel electrodes to thereby form the second storage capacitors.20. The thin film transistor array panel of claim 19 wherein the storagecapacitor electrode patterns are formed within pixel regions defined bythe gate lines and the data lines.
 21. The thin film transistor arraypanel of claim 19 wherein the storage capacitor electrode patterns areformed with a bar shape along the data lines while being overlapped withperipheral portions of the pixel electrodes.
 22. A liquid crystaldisplay comprising: the thin film transistor array panel of claim 17; acounter substrate facing the thin film transistor array panel; and aliquid crystal layer sandwiched between the thin film transistor arraypanel and the counter panel.
 23. The liquid crystal display of claim 22wherein the first and the second storage capacitors have anelectrostatic capacitance greater than the electrostatic capacitance ofthe liquid crystal layer by 90% or more.
 24. A thin film transistorarray panel comprising: an insulating substrate; a gate line assemblyformed on the insulating substrate, the gate line assembly having firstgate lines, gate electrodes connected to the first gate lines, andsecond gate lines spaced apart from the first gate lines with apredetermined distance; a gate insulating layer covering the gate lineassembly; a semiconductor pattern formed on the gate insulating layerwhile being overlapped with the gate electrodes; a data line assemblyand storage capacitor conductive patterns formed on the gate insulatinglayer overlaid with the semiconductor pattern, the data line assemblyhaving data lines crossing over the first and the second gate lines,source electrodes and drain electrodes, the storage capacitor conductivepatterns being partially overlapped with the second gate lines tothereby form first storage capacitors; a passivation layer covering thedata line assembly, the storage capacitor conductive patterns and thesemiconductor pattern; first and second contact holes formed at thepassivation layer while exposing the drain electrodes and the storagecapacitor conductive patterns, respectively; and pixel electrodes formedat the passivation layer while being connected to the drain electrodesand the storage capacitor conductive patterns through the first and thesecond contact holes, the pixel electrodes being partially overlappedwith the second gate lines to thereby form second storage capacitors.25. A liquid crystal display comprising: the thin film transistor arraypanel of claim 24; a counter substrate facing the thin film transistorarray panel; and a liquid crystal layer sandwiched between the thin filmtransistor array panel and the counter panel.
 26. The liquid crystaldisplay of claim 25 wherein the first and the second storage capacitorshave an electrostatic capacitance greater than the electrostaticcapacitance of the liquid crystal layer by 90% or more.
 27. A thin filmtransistor array panel comprising: an insulating substrate; a gate lineassembly and storage capacitor electrode lines formed on the insulatingsubstrate, the gate line assembly having gate lines and gate electrodes;a gate insulating layer covering the gate line assembly and the storagecapacitor electrode lines; first contact holes formed at the gateinsulating layer while exposing the storage capacitor electrode lines; asemiconductor pattern formed on the gate insulating layer while beingoverlapped with the gate electrodes; a data line assembly and storagecapacitor conductive patterns formed on the gate insulating layeroverlaid with the semiconductor pattern, the data line assembly havingdata lines, source electrodes and drain electrodes, the storagecapacitor conductive patterns being connected to the storage capacitorelectrode lines through the first contact holes; a passivation layercovering the data line assembly, the storage capacitor conductivepatterns and the semiconductor pattern; second contact holes formed atthe passivation layer while exposing the drain electrodes; and pixelelectrodes formed at the passivation layer while being connected to thedrain electrodes through the second contact holes, the pixel electrodesbeing overlapped with the storage capacitor conductive patterns tothereby form first storage capacitors while being partially overlappedwith the storage capacitor electrode lines to thereby form secondstorage capacitors.
 28. The thin film transistor array panel of claim 27wherein the storage capacitor electrode lines proceed parallel to thegate lines.
 29. The thin film transistor array panel of claim 27 whereinthe storage capacitor conductive patterns are overlapped with thestorage capacitor electrode lines.
 30. The thin film transistor arraypanel of claim 29 wherein the storage capacitor conductive patterns areformed within pixel regions defined by the gate lines and the datalines.
 31. The thin film transistor array panel of claim 27 wherein thestorage capacitor electrode patterns are formed with a bar shape alongthe data lines while being overlapped with peripheral portions of thepixel electrodes.
 32. A liquid crystal display comprising: the thin filmtransistor array panel of claim 27; a counter substrate facing the thinfilm transistor array panel; and a liquid crystal layer sandwichedbetween the thin film transistor array panel and the counter panel. 33.The liquid crystal display of claim 32 wherein the first and the secondstorage capacitors have an electrostatic capacitance greater than theelectrostatic capacitance of the liquid crystal layer by 90% or more.34. A thin film transistor array panel comprising: an insulatingsubstrate; a gate line assembly formed on the insulating substrate, thegate line assembly having first gate lines, gate electrodes connected tothe first gate lines, and second gate lines spaced apart from the firstgate lines with a predetermined distance; a gate insulating layercovering the gate line assembly; first contact holes formed at the gateinsulating layer while partially exposing the second gate lines; asemiconductor pattern formed on the gate insulating layer while beingoverlapped with the gate electrodes; a data line assembly and storagecapacitor conductive patterns formed on the gate insulating layeroverlaid with the semiconductor pattern, the data line assembly havingdata lines crossing over the first and the second gate lines, sourceelectrodes and drain electrodes, the storage capacitor conductivepatterns being connected to the second gate lines through the firstcontact holes; a passivation layer covering the data line assembly, thestorage capacitor conductive patterns and the semiconductor pattern;second contact holes formed at the passivation layer while exposing thedrain electrodes; and pixel electrodes formed at the passivation layerwhile being connected to the drain electrodes through the second contactholes, the pixel electrodes being overlapped with the storage capacitorconductive patterns to thereby form first storage capacitors while beingpartially overlapped with the second gate lines to thereby form secondstorage capacitors.
 35. A liquid crystal display comprising: the thinfilm transistor array panel of claim 34; a counter substrate facing thethin film transistor array panel; and a liquid crystal layer sandwichedbetween the thin film transistor array panel and the counter panel. 36.The liquid crystal display of claim 35 wherein the first and the secondstorage capacitors have an electrostatic capacitance greater than theelectrostatic capacitance of the liquid crystal layer by 90% or more.37. A method of fabricating a thin film transistor array panel, themethod comprising the steps of: forming a gate line assembly and astorage capacitor line assembly on an insulating substrate such that thegate line assembly has gate lines and gate electrodes; forming a gateinsulating layer such that the gate insulating layer covers the gateline assembly and the storage capacitor line assembly; forming asemiconductor pattern on the gate insulating layer; forming a data lineassembly and storage capacitor conductive patterns on the gateinsulating layer overlaid with the semiconductor pattern such that thedata line assembly has data lines, source electrodes and drainelectrodes, and the storage capacitor conductive patterns are partiallyoverlapped with the storage capacitor line assembly to thereby formfirst storage capacitors; forming a passivation layer such that thepassivation layer covers the data line assembly, the storage capacitorconductive patterns and the semiconductor pattern; forming first andsecond contact holes at the passivation layer such that the first andthe second contact holes expose the drain electrodes and the storagecapacitor conductive patterns, respectively; and forming pixelelectrodes on the passivation layer such that the pixel electrodes areconnected to the drain electrodes and the storage capacitor conductivepatterns through the first and the second contact holes while formingsecond storage capacitors in association with parts of the storagecapacitor lines assembly.
 38. The method of claim 37 wherein the storagecapacitor line assembly has storage capacitor electrode lines proceedingparallel to the gate lines, and storage capacitor electrode patternsconnected to the storage capacitor electrode lines.
 39. A method offabricating a thin film transistor array panel, the method comprisingthe steps of: forming a gate line assembly on an insulating substratesuch that the gate line assembly has first gate lines, gate electrodesconnected to the first gate lines, and second gate lines spaced apartfrom the first gate lines with a predetermined distance while proceedingparallel to the first gate lines; forming a gate insulating layer suchthat the gate insulating layer covers the gate line assembly; forming asemiconductor pattern on the gate insulating layer such that thesemiconductor pattern is overlapped with the gate electrodes; forming adata line assembly and storage capacitor conductive patterns on the gateinsulating layer overlaid with the semiconductor pattern such that thedata line assembly has data lines crossing over the first and the secondgate lines, source electrodes and drain electrodes, and the storagecapacitor conductive patterns are partially overlapped with the secondgate lines to thereby form first storage capacitors; forming apassivation layer such that the passivation layer covers the data lineassembly, the storage capacitor conductive patterns and thesemiconductor pattern; forming first and second contact holes at thepassivation layer such that the first and the second contact holesexpose the drain electrodes and the storage capacitor conductivepatterns, respectively; and forming pixel electrodes on the passivationlayer such that the pixel electrodes are connected to the drainelectrodes and the storage capacitor conductive patterns through thefirst and the second contact holes while forming second storagecapacitors in association with parts of the second gate lines.
 40. Amethod of fabricating a thin film transistor array panel, the methodcomprising the steps of: forming a gate line assembly and storagecapacitor electrode lines on an insulating substrate such that the gateline assembly has gate lines and gate electrodes; forming a gateinsulating layer such that the gate insulating layer covers the gateline assembly and the storage capacitor electrode lines; forming firstcontact holes at the gate insulating layer such that the first contactholes expose the storage capacitor electrode lines; forming asemiconductor pattern on the gate insulating layer such that thesemiconductor pattern is overlapped with the gate electrodes; forming adata line assembly and storage capacitor conductive patterns on the gateinsulating layer overlaid with the semiconductor pattern such that thedata line assembly has data lines, source electrodes and drainelectrodes, and the storage capacitor conductive patterns are connectedto the storage capacitor electrode lines through the first contactholes; forming a passivation layer such that the passivation layercovers the data line assembly, the storage capacitor conductive patternsand the semiconductor pattern; forming second contact holes at thepassivation layer such that the second contact holes expose the drainelectrodes; and forming pixel electrodes on the passivation layer suchthat the pixel electrodes are connected to the drain electrodes throughthe second contact holes, the pixel electrodes being overlapped with thestorage capacitor conductive patterns to thereby form first storagecapacitors while being partially overlapped with the storage capacitorelectrode lines to thereby form second storage capacitors.
 41. A methodof fabricating a thin film transistor array panel, the method comprisingthe steps of: forming a gate line assembly on an insulating substratesuch that the gate line assembly has first gate lines, gate electrodesconnected to the first gate lines, and second gate lines spaced apartfrom the first gate lines with a predetermined distance while proceedingparallel to the first gate lines; forming a gate insulating layer suchthat the gate insulating layer covers the gate line assembly; formingfirst contact holes at the gate insulating layer such that the firstcontact holes partially expose the second gate lines; forming asemiconductor pattern on the gate insulating layer such that thesemiconductor pattern is overlapped with the gate electrodes; forming adata line assembly and storage capacitor conductive patterns on the gateinsulating layer overlaid with the semiconductor pattern such that thedata line assembly has data lines crossing over the first and the secondgate lines, source electrodes and drain electrodes, and the storagecapacitor conductive patterns are connected to the second gate linesthrough the first contact holes; forming a passivation layer such thatthe passivation layer covers the data line assembly, the storagecapacitor conductive patterns and the semiconductor pattern; formingsecond contact holes at the passivation layer such that the secondcontact holes expose the drain electrodes; and forming pixel electrodeson the passivation layer such that the pixel electrodes are connected tothe drain electrodes through the second contact holes, the pixelelectrodes being overlapped with the storage capacitor conductivepatterns to thereby form first storage capacitors while being partiallyoverlapped with the second gate lines to thereby form second storagecapacitors.